uvm - uvm_port_base class derivation correct hierarchy -


enter image description here

the above 2 diagrams contradicting. can please clarify correct class inheritence class? below mentioned link both in sequential order

https://www.dvteclipse.com/uvm-1.2_public_api/uvm_pkg-uvm_port_base.html

it little sneaky because both true. looking @ source, first line declare uvm_port_base

virtual class uvm_port_base #(type if=uvm_void) extends if;

uvm_port_base inherits if, parameter. default value of if uvm_void.

for example, many tlm classes override parameter class extend from. example:

class uvm_blocking_put_export #(type t=int)   extends uvm_port_base #(uvm_tlm_if_base #(t,t));

uvm_tlm_if_base extends form uvm_if_base_abstract, extends uvm_report_object, extends uvm_object, extends uvm_void. uvm_blocking_put_export still has uvm_void parent got added functionality added other parents. redirected inheritance work around multiple inheritance challenge language can support single inheritance*.

*as of 2012 release, systemverilog added multiple inheritance approach inspired/borrowed/similar-to java's approach issue, adding interface class , implements. not major simulator vendor haven't implemented improvement. i'm guessing uvm overhauled , utilizes these features after simulator support feature mainstream.


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