signals - VHDL: why is NOT 'Z' = 'X' -

in vhdl, why is:

not 'z' = 'x'  

where z high impedence , x unknown (see std_logic signal types below).

context: applicable vhdl. given exam question 'z' signal sent through inverter , yielded 'x'. not understand why occurs , why answer not 'z'.

'u': uninitialized. (signal hasn't been set yet) 'x': unknown (impossible determine value/result) '0': logic 0 '1': logic 1 'z': high impedance (signal source when source makes no effective contribution resolved value of signal) 'w': weak unknown signal (can't tell if should 0 or 1) 'l': weak signal should go 0 'h': weak signal should go 1 '-': don't care  

(i have made comment can't) in context of have said, if input inverter (or component matter) 'z' (driving high impedence), expect output be? result must fall within set of defined values std_logic signal.

if no value being driven on input inverter (ie. there 1 signal driving input, , 'z'), simulator not able resolve input value, results in unknown output ('x').

edit:

as user1155120 pointed out in documents linked, behaviour occurs due declared "not_table" in std_logic_1164-body, states following mapping:

-- truth table "not" function   constant not_table : stdlogic_1d :=     --  -------------------------------------------------     --  |   u    x    0    1    z    w    l    h    -   |     --  -------------------------------------------------           ('u', 'x', '1', '0', 'x', 'x', '1', '0', 'x');